* gnetlist -g spice-sdb -o t.net t.sch ********************************************************* * Spice file generated by gnetlist * * spice-sdb version 4.28.2007 by SDB -- * * provides advanced spice netlisting capability. * * Documentation at http://www.brorson.com/gEDA/SPICE/ * ********************************************************* *vvvvvvvv Included SPICE model from dtrigger.lib vvvvvvvv .SUBCKT DTRIGGER Data Clock Q nQ CLR Vcc GND .SUBCKT NAND IN1 IN2 OUT Vcc GND .model nMOSe nmos (vto=1) .model pMOSe pmos (vto=-1) MQ7 OUT IN1 2 2 nMOSe MQ8 2 IN2 GND GND nMOSe MQ6 OUT IN2 Vcc Vcc pMOSe MQ5 OUT IN1 Vcc Vcc pMOSe .ENDS NAND R1 GND S 1g R2 Vcc R 1g XU13 9 9 2 Vcc GND NAND XU12 4 CLR 9 Vcc GND NAND XU10 Clock Clock 5 Vcc GND NAND XU3 Data Data 8 Vcc GND NAND XU4 5 8 7 Vcc GND NAND XU1 Data 5 6 Vcc GND NAND XU5 S 7 R Vcc GND NAND XU2 6 R S Vcc GND NAND XU11 5 5 3 Vcc GND NAND XU8 3 R 4 Vcc GND NAND XU6 S 3 1 Vcc GND NAND XU9 Q 2 nQ Vcc GND NAND XU7 1 nQ Q Vcc GND NAND .ENDS DTRIGGER *^^^^^^^^ End of included SPICE model from dtrigger.lib ^^^^^^^^ * *============== Begin SPICE netlist of main design ============ .ic v(CLR)=0 C1 0 CLR 0.1u R1 CLR Vcc 10k R2 0 OUT2 1g XU2 2 OUT2 OUT4 2 CLR Vcc 0 DTRIGGER V2 Clock 0 pulse 0 3 1 1p 1p 1 2 XU1 1 Clock OUT2 1 CLR Vcc 0 DTRIGGER V1 Vcc 0 3 .end