v 20130925 2 C 40000 40000 0 0 0 title-B.sym C 49600 45200 1 0 0 spice-model-1.sym { T 49700 45900 5 10 0 1 0 0 1 device=model T 49700 45800 5 10 1 1 0 0 1 refdes=A1 T 50900 45500 5 10 1 1 0 0 1 model-name=LT1007 T 50100 45300 5 10 1 1 0 0 1 file=LT1007CS.txt } C 48700 48100 1 0 0 voltage-3.sym { T 48900 48800 5 8 0 0 0 0 1 device=VOLTAGE_SOURCE T 48900 48600 5 10 1 1 180 0 1 refdes=V1 T 49600 48600 5 10 1 1 180 0 1 value=15 } C 51500 46700 1 0 0 gnd-1.sym N 50700 47000 51600 47000 4 C 49800 46900 1 0 0 resistor-2.sym { T 50200 47250 5 10 0 0 0 0 1 device=RESISTOR T 50000 47200 5 10 1 1 0 0 1 refdes=R T 50300 47200 5 10 1 1 0 0 1 value=1k } N 49000 47000 49800 47000 4 { T 49200 47200 5 10 1 1 0 0 1 netname=OUT } C 47900 46500 1 0 0 opamp-2.sym { T 48700 47500 5 10 0 0 0 0 1 device=OPAMP T 47600 47500 5 10 1 1 0 0 1 refdes=U1 T 48700 47700 5 10 0 0 0 0 1 symversion=0.1 T 48700 46400 5 10 1 1 0 0 1 model-name=LT1007 } C 48300 46000 1 0 0 gnd-1.sym C 45600 45100 1 0 0 vpwl-1.sym { T 46300 45750 5 10 1 1 0 0 1 refdes=Vin T 46300 45950 5 10 0 0 0 0 1 device=vpwl T 46300 46150 5 10 0 0 0 0 1 footprint=none T 46300 45550 5 10 1 1 0 0 1 value=pwl 0 0 1m 6 2m 4 3m 6 4m 0 } N 48400 46500 48400 46300 4 N 48200 48300 48700 48300 4 N 48400 48300 48400 47500 4 C 49800 47700 1 0 0 gnd-1.sym N 49600 48300 49900 48300 4 N 49900 48300 49900 48000 4 C 45800 44700 1 0 0 gnd-1.sym C 48200 48400 1 180 0 resistor-2.sym { T 47800 48050 5 10 0 0 180 0 1 device=RESISTOR T 47700 48600 5 10 1 1 180 0 1 refdes=Rf2 T 48200 48600 5 10 1 1 180 0 1 value=100k } C 46000 48200 1 0 0 resistor-2.sym { T 46400 48550 5 10 0 0 0 0 1 device=RESISTOR T 46400 48600 5 10 1 1 180 0 1 refdes=Rf1 T 46800 48600 5 10 1 1 180 0 1 value=50k } C 45800 47900 1 0 0 gnd-1.sym N 47900 47300 45900 47300 4 { T 45800 47400 5 10 1 1 0 0 1 netname=IN } N 45900 47300 45900 46300 4 N 47100 48300 47100 46700 4 N 47100 46700 47900 46700 4 N 46900 48300 47300 48300 4 N 45900 48300 45900 48200 4 N 45900 45100 45900 45000 4 N 46000 48300 45900 48300 4